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;
; interrupt
;
org 0038h
SAT equ 0x1b00 ; Sprite Attribute Table
global _vdps0, _curr_plan, _n_sprt, _sprt, _ready
; RST 38 handler
ex af,af'
exx
ld a,(_ready) ; no action if not ready
or a
in a,(0x99)
ld (_vdps0),a
jp z,_end
bit 06h,a
jp z,3f
and 31
add a,a
add a,a
ld b,a
ld a,(_curr_plan)
add a,b
ld e,a ; curr_plan + = (vdps0 & 31)*4;
ld a,(_n_sprt)
ld c,a
; In A rest of E / C
ld a,e
1: sub c
jp nc,1b
add a,c
jp z,3f
ld (_curr_plan),a ; curr_plan -= (curr_plan/(n_sprt)) * (n_sprt);
ld e,a
ld a,SAT & 255
out (0x99),a
ld a,SAT/256 | 64
out (0x99),a
ld hl,_sprt
ld d,0
add hl,de ; hl = sprt + curr_plan
ld c,0x98
ld a,(_n_sprt)
sub e
ld b,a ; b = n_sprt -curr_plan
otir
ld hl,_sprt ; hl = sprt
ld b,e ; b = curr_plan
otir
jp 1f
3:
ld a,SAT & 255
out (0x99),a
ld a,SAT/256 | 64
out (0x99),a
xor a
ld (_curr_plan),a
ld hl,_sprt
ld c,0x98
ld a,(_n_sprt)
ld b,a
otir
1:
ld a,208
out (0x98),a
xor a
ld (_ready),a
_end:
ex af,af'
exx
ei
ret
Some explanations:
The vdp status register holds the plane of the 5th sprite, the best method for reordering the
sprite is to plot on plane 0 (the max priority) the sprite whose plane was indicated by the status
register as 5th sprite.
Some variables:
sprt is the 32*4=128 copy of the SAT in RAM,
n_sprt holds the number of valid bytes in sprt,
curr_plan is the VDP sprite plan in sprt that is currently mapped on plane 0 (max priority)
Note: you need to set set "_ready" to 1 at each interrupt, each time you update the SAT.
This part is unessential and could be skipped, the sole reason for having a "_ready" signal is to
avoid that the the routine that writes in the SAT in RAM has not jet completed its update when
the int occurs.
The best way to handle this kind of issues is to have a double SAT in RAM, one for sprite scramble,
one to be updated by the main.
When update is finished you swap the two SAT, but this routine is still under development...